Remarks
The supported features and CPU type information is returned in CPUInfo, an array of four 32-bit integers that is filled with the values of the EAX, EBX, ECX, and EDX registers (in that order) after the cpuid instruction is called. The information returned has a different meaning depending on the value passed as the InfoType parameter. The information returned with various values of InfoType is processor-dependent.
When the InfoType argument is 0, the following table describes the output.
Information Returned
Array index Bit range Description
0
0-31
Maximum meaningful value for the InfoType parameter.
1
0-31
Identification String (part 1)
2
0-31
Identification String (part 3)
3
0-31
Identification String (part 2)
When the InfoType argument is 1, the following table describes the output.
CPU Information Returned
Array index Bit range Description
0
0-3
Stepping ID
0
4-7
Model
0
8-11
Family
0
12-13
Processor Type
0
14-15
Reserved
0
16-19
Extended model
0
20-27
Extended family
0
28-31
Reserved
1
0-7
Brand Index
1
8-15
CLFLUSH cache line size / 8
1
16-23
Reserved
1
24-31
APIC Physical ID
2
0
SSE3 New Instructions
2
1-2
Reserved
2
3
MONITOR/MWAIT
2
4
CPL Qualified Debug Store
2
5-7
Reserved
2
8
Thermal Monitor 2
2
9
Reserved
2
10
L1 Context ID
2
11-31
Reserved
3
0-31
Feature Information (see below)
The following table shows the meaning of the Feature Information value, the value of EDX which is written to CPUInfo[3], when the InfoType argument is 1.
Feature Information Returned
Bit Mnemonic Description
0
FPU
x87 FPU on Chip
1
VME
Virtual-8086 Mode Enhancement
2
DE
Debugging Extensions
3
PSE
Page Size Extensions
4
TSC
Time Stamp Counter
5
MSR
RDMSR and WRMSR Support
6
PAE
Physical Address Extensions
7
MCE
Machine Check Exception
8
CX8
CMPXCHG8B Inst.
9
APIC
APIC on Chip
10
n/a
Reserved
11
SEP
SYSENTER and SYSEXIT
12
MTRR
Memory Type Range Registers
13
PGE
PTE Global Bit
14
MCA
Machine Check Architecture
15
CMOV
Conditional Move/Compare Instruction
16
PAT
Page Attribute Table
17
PSE
Page Size Extension
18
PSN
Processor Serial Number
19
CLFSH
CFLUSH Instruction
20
n/a
Reserved
21
DS
Debug Store
22
ACPI
Thermal Monitor and Clock Ctrl
23
MMX
MMX Technology
24
FXSR
FXSAVE/FXRSTOR
25
SSE
SSE Extensions
26
SSE2
SSE2 Extensions
27
SS
Self Snoop
28
HTT
Hyper-threading technology
29
TM
Thermal Monitor
30
n/a
Reserved
31
PBE
Pend. Brk. En.
Some processors, such as the SSE3-enabled processors, support additional InfoType values. When the InfoType argument is 3 or 4, these processors might return cache and TLB information. When InfoType is 5, these processors return information relating to the monitor feature (see _mm_monitor).
The SSE3-enabled processors support Extended Function CPUID information. If this is supported, InfoType values from 0x8000000 might be used to return information. To determine the maximum meaningful value allowed, set InfoType to 0x8000000. The maximum value of InfoType supported will be written to CPUInfo[0]. The following table shows values returned using the extended function CPUID information.
Extended Function CPUID Information Returned
InfoType Array index Information
0x80000000
0
Maximum meaningful value of InfoType for extended function CPUID information.
0x80000000
1-3
Reserved.
0x80000001
0-4
Reserved
0x80000002
0-4
Processor Brand String
0x80000003
0-4
Processor Brand String, continued
0x80000004
0-4
Processor Brand String, continued
0x80000005
0-4
Reserved
0x80000006
0-1
Reserved
0x80000006
2
Bits 0-7: Cache Line Size
Bits 12-15: L2 Associativity
Bits 16-31: Cache size in 1K units
0x80000006
3
Reserved
0x80000007
0-4
Reserved
Example
Copy Code
// cpuid.cpp
// processor: x86, x64
// Use the __cpuid intrinsic to get information about a CPU
const char* szFeatures[] =
{
"x87 FPU On Chip",
"Virtual-8086 Mode Enhancement",
"Debugging Extensions",
"Page Size Extensions",
"Time Stamp Counter",
"RDMSR and WRMSR Support",
"Physical Address Extensions",
"Machine Check Exception",
"CMPXCHG8B Instruction",
"APIC On Chip",
"Unknown1",
"SYSENTER and SYSEXIT",
"Memory Type Range Registers",
"PTE Global Bit",
"Machine Check Architecture",
"Conditional Move/Compare Instruction",
"Page Attribute Table",
"Page Size Extension",
"Processor Serial Number",
"CFLUSH Extension",
"Unknown2",
"Debug Store",
"Thermal Monitor and Clock Ctrl",
"MMX Technology",
"FXSAVE/FXRSTOR",
"SSE Extensions",
"SSE2 Extensions",
"Self Snoop",
"Hyper-threading Technology",
"Thermal Monitor",
"Unknown4",
"Pend. Brk. EN."
};
int main(int argc, char* argv[])
{
char CPUString[0x20];
char CPUBrandString[0x40];
int CPUInfo[4] = {-1};
int nSteppingID = 0;
int nModel = 0;
int nFamily = 0;
int nProcessorType = 0;
int nExtendedmodel = 0;
int nExtendedfamily = 0;
int nBrandIndex = 0;
int nCLFLUSHcachelinesize = 0;
int nAPICPhysicalID = 0;
int nFeatureInfo = 0;
int nCacheLineSize = 0;
int nL2Associativity = 0;
int nCacheSizeK = 0;
int nRet = 0;
unsigned nIds, nExIds, i;
bool bSSE3NewInstructions = false;
bool bMONITOR_MWAIT = false;
bool bCPLQualifiedDebugStore = false;
bool bThermalMonitor2 = false;
// __cpuid with an InfoType argument of 0 returns the number of
// valid Ids in CPUInfo[0] and the CPU identification string in
// the other three array elements. The CPU identification string is
// not in linear order. The code below arranges the information
// in a human readable form.
__cpuid(CPUInfo, 0);
nIds = CPUInfo[0];
memset(CPUString, 0, sizeof(CPUString));
*((int*)CPUString) = CPUInfo[1];
*((int*)(CPUString+4)) = CPUInfo[3];
*((int*)(CPUString+8)) = CPUInfo[2];
// Get the information associated with each valid Id
for (i=0; i<=nIds; ++i)
{
__cpuid(CPUInfo, i);
printf_s("\nFor InfoType %d\n", i);
printf_s("CPUInfo[0] = 0x%x\n", CPUInfo[0]);
printf_s("CPUInfo[1] = 0x%x\n", CPUInfo[1]);
printf_s("CPUInfo[2] = 0x%x\n", CPUInfo[2]);
printf_s("CPUInfo[3] = 0x%x\n", CPUInfo[3]);
// Calling __cpuid with 0x80000000 as the InfoType argument
// gets the number of valid extended IDs.
__cpuid(CPUInfo, 0x80000000);
nExIds = CPUInfo[0];
memset(CPUBrandString, 0, sizeof(CPUBrandString));
// Get the information associated with each extended ID.
for (i=0x80000000; i<=nExIds; ++i)
{
__cpuid(CPUInfo, i);
printf_s("\nFor InfoType %x\n", i);
printf_s("CPUInfo[0] = 0x%x\n", CPUInfo[0]);
printf_s("CPUInfo[1] = 0x%x\n", CPUInfo[1]);
printf_s("CPUInfo[2] = 0x%x\n", CPUInfo[2]);
printf_s("CPUInfo[3] = 0x%x\n", CPUInfo[3]);
// Interpret CPU brand string and cache information.
if (i == 0x80000002)
memcpy(CPUBrandString, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000003)
memcpy(CPUBrandString + 16, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000004)
memcpy(CPUBrandString + 32, CPUInfo, sizeof(CPUInfo));
else if (i == 0x80000006)
{
nCacheLineSize = CPUInfo[2] & 0xff;
nL2Associativity = (CPUInfo[2] >> 12) & 0xf;
nCacheSizeK = (CPUInfo[2] >> 16) & 0xffff;
}
}
// Display all the information in user-friendly format.
printf_s("\n\nCPU String: %s\n", CPUString);
if (nIds >= 1)
{
if (nSteppingID)
printf_s("Stepping ID = %d\n", nSteppingID);
if (nModel)
printf_s("Model = %d\n", nModel);
if (nFamily)
printf_s("Family = %d\n", nFamily);
if (nProcessorType)
printf_s("Processor Type = %d\n", nProcessorType);
if (nExtendedmodel)
printf_s("Extended model = %d\n", nExtendedmodel);
if (nExtendedfamily)
printf_s("Extended family = %d\n", nExtendedfamily);
if (nBrandIndex)
printf_s("Brand Index = %d\n", nBrandIndex);
if (nCLFLUSHcachelinesize)
printf_s("CLFLUSH cache line size = %d\n",
nCLFLUSHcachelinesize);
if (nAPICPhysicalID)
printf_s("APIC Physical ID = %d\n", nAPICPhysicalID);
if (nFeatureInfo || bSSE3NewInstructions ||
bMONITOR_MWAIT || bCPLQualifiedDebugStore ||
bThermalMonitor2)
{
printf_s("\nThe following features are supported:\n");
if (bSSE3NewInstructions)
printf_s("\tSSE3 New Instructions\n");
if (bMONITOR_MWAIT)
printf_s("\tMONITOR/MWAIT\n");
if (bCPLQualifiedDebugStore)
printf_s("\tCPL Qualified Debug Store\n");
if (bThermalMonitor2)
printf_s("\tThermal Monitor 2\n");
i = 0;
nIds = 1;
while (i < (sizeof(szFeatures)/sizeof(const char*)))
{
if (nFeatureInfo & nIds)
{
printf_s("\t");
printf_s(szFeatures[i]);
printf_s("\n");
}
nIds <<= 1;
++i;
}
}
}
if (nExIds >= 0x80000004)
printf_s("\nCPU Brand String: %s\n", CPUBrandString);
CPU String: GenuineIntel
Stepping ID = 1
Model = 3
Family = 15
CLFLUSH cache line size = 64
The following features are supported:
SSE3 New Instructions
MONITOR/MWAIT
CPL Qualified Debug Store
x87 FPU On Chip
Virtual-8086 Mode Enhancement
Debugging Extensions
Page Size Extensions
Time Stamp Counter
RDMSR and WRMSR Support
Physical Address Extensions
Machine Check Exception
CMPXCHG8B Instruction
APIC On Chip
SYSENTER and SYSEXIT
Memory Type Range Registers
PTE Global Bit
Machine Check Architecture
Conditional Move/Compare Instruction
Page Attribute Table
Page Size Extension
CFLUSH Extension
Debug Store
Thermal Monitor and Clock Ctrl
MMX Technology
FXSAVE/FXRSTOR
SSE Extensions
SSE2 Extensions
Self Snoop
Hyper-threading Technology
Thermal Monitor
Pend. Brk. EN.
CPU Brand String: Genuine Intel(R) CPU 2.80GHz
Cache Line Size = 64
L2 Associativity = 8
Cache Size = 1024K
