这个PPT以前我也看过,里面提到的 MTRRs 方法有篇论文《Attacking SMM Memory via Intel® CPU Cache Poisoning》专门谈过,Windows下不行。
改写SMBASE重新映射SMM内存我虚拟机中没试出来,也许他们模拟得都没那么完善(实际上VM6中光触发SMI就不知飞哪去了)。
这是关于改写SMBASE的一段资料(已经忘了从哪抄出来的了),有兴趣的继续
The attacker has to modify the caching strategy of the SMRAM location (example if SMBASE=0xa0000). "movl $0x06060606, %eax" "movl $0x0, %edx" "movl $0x259, $ecx" "wrmsr"
Objection: But wait! Only the data cache is modified, not the instruction cache, so the modification should have no effect.
True, but the instruction caches will probably be flushed during mode transitions as running 16-bit instructions in a 32-bit (or 64-bit) mode should not be advised. In that case, instructions are reloaded from… the L1 data cache.
The SMI handler can flush the cache before exiting! No SMI handler that I have seen does that. Anyway if the handler did so it would not be a major problem as cache flushing only ensures SMI handler confidentiality (not integrity).
CPU SMBASE register (SMI handler base address SMBASE+0x8000)
1. 关于SMM Handler 也就是进入SMM后开始执行的位置,该位置默认为 SMBASE+0x8000,即(0xA8000)处。一段对此阐述比较详细的话: This is how it works:
During the boot process the BIOS places a temporary SMM handler at the default location, 00038000h. This consists of the default SMBASE value of 00030000h plus the default (fixed) SMM entry offset of 8000h.
This temporary SMM handler does nothing but placing a new SMBASE value in the SMBASE field of the state save map, and then it RSMs. As a part of the RSM this new SMBASE value gets loaded into the processor.
Then the BIOS places the final SMM handler at the final location. With Intel chipsets that usually is 000A8000h, ie. it uses DRAM which would have to be remapped otherwise, since it is "underneath" VRAM.
To ensure that this final SMM handler works fine, a BIOS usually would assert SMI# once more.
Placing such a temporary SMM handler doesn't require anything special. However, placing the final SMM handler does, since its memory is over- lapping other memmory for most chipsets. The chipsets provide bits, so that the programmer can select which memory is visible/accessed, and a few chipsets even provide the ability to protect the SMM handler until the next RESET, so that nobody can overwrite it.