最近又搞了个cortex m0+ soc源码，只分享cortex m0+部分。能力强的可以用于更接近硬件级的代码仿真，比如自己搭soc然后用synopsys的仿真工具进行仿真。

综合时会提示缺少cm0p_acg.v文件，该模块的功能是生成时钟。文件内容如下：
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2008-2012 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Checked In : Date:2011−12−3017:59:54+0000(Fri,30Dec2011)
// Revision : Revision:196408
// Release : Cortex-M0+ AT590-r0p1-00rel0
//
//-----------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//-----------------------------------------------------------------------------

module cm0p_acg
(input wire CLKIN,
input wire ENABLE,
input wire DFTSE,
output wire CLKOUT);

// -------------------------------------------------------------------------
// NOTE: THIS MODULE IS NOT INTENDED FOR USE IN SYNTHESIS.
// IF ARCHITECTURAL CLOCK GATING IS REQUIRED, THEN IT IS STRONGLY
// RECOMMENDED THAT AN EQUIVALENT MODULE DIRECTLY INSTANTIATING YOUR
// TARGET LIBRARY'S ICG CELL IS USED IN PLACE OF THIS SIMULATION
// MODEL.
//
// If architectural clock gating is not required, configured by the
// processor ACG parameter being 0, then this module will not be used.
// -------------------------------------------------------------------------

// -------------------------------------------------------------------------
// Simulation model of clock gate cell
// -------------------------------------------------------------------------

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