* 1.1 OVERVIEW
* 1.2 WHAT IS A STACK?
o 1.2.1 Cafeteria tray example
o 1.2.2 Example software implementations
o 1.2.3 Example hardware implementations
* 1.3 WHY ARE STACK MACHINES IMPORTANT?
* 1.4 WHY ARE STACKS USED IN COMPUTERS?
o 1.4.1 Expression evaluation stack
o 1.4.2 The return address stack
o 1.4.3 The local variable stack
o 1.4.4 The parameter stack
o 1.4.5 Combination stacks
* 1.5 THE NEW GENERATION OF STACK COMPUTERS
* 1.6 HIGHLIGHTS FROM THE REST OF THE BOOK
CHAPTER 2: A Taxonomy of Hardware Stack Support
* 2.1 THE THREE AXIS STACK DESIGN SPACE
o 2.1.1 Single vs. multiple stacks
o 2.1.2 Size of stack buffers
o 2.1.3 0-, 1-, and 2-operand addressing
* 2.2 TAXONOMY NOTATION AND CATEGORIES
o 2.2.1 Notation
o 2.2.2 List of the categories in the design space
* 2.3 INTERESTING POINTS IN THE TAXONOMY.
CHAPTER 3: Multiple-stack, 0-operand Machines
* 3.1 WHY THESE MACHINES ARE INTERESTING
* 3.2 A GENERIC STACK MACHINE
o 3.2.1 Block diagram
+ 3.2.1.1 Data bus
+ 3.2.1.2 Data stack
+ 3.2.1.3 Return stack
+ 3.2.1.4 ALU and top-of-stack register
+ 3.2.1.5 Program counter
+ 3.2.1.6 Program memory
+ 3.2.1.7 I/O
o 3.2.2 Data operations
+ 3.2.2.1 Reverse Polish Notation
+ 3.2.2.2 Arithmetic and logical operators
+ 3.2.2.3 Stack manipulation operators
+ 3.2.2.4 Memory fetching and storing
+ 3.2.2.5 Literals
o 3.2.3 Instruction execution
+ 3.2.3.1 Program Counter
+ 3.2.3.2 Conditional branching
+ 3.2.3.3 Subroutine calls
+ 3.2.3.4 Hardwired vs. microcoded instructions
o 3.2.4 State changing
+ 3.2.4.1 Stack overflow/underflow interrupts
+ 3.2.4.2 I/O service interrupts
+ 3.2.4.3 Task switching
* 3.3 OVERVIEW OF THE FORTH PROGRAMMING LANGUAGE
o 3.3.1 Forth as a common thread
o 3.3.2 The Forth virtual machine
+ 3.3.2.1 Stack architecture/RPN
+ 3.3.2.2 Short, frequent procedure calls
o 3.3.3 Emphasis on interactivity, flexibility
CHAPTER 4: Architecture of 16-bit Systems
* 4.1 CHARACTERISTICS OF 16-BIT DESIGNS
o 4.1.1 Good fit with the traditional Forth model
o 4.1.2 Smallest interesting width
o 4.1.3 Small size allows integrated embedded system
* 4.2 ARCHITECTURE OF THE WISC CPU/16
o 4.2.2 Block diagram
o 4.2.3 Instruction set summary
o 4.2.4 Architectural features
o 4.2.5 Implementation and featured application areas
* 4.3 ARCHITECTURE OF THE MISC M17
o 4.3.2 Block diagram
o 4.3.3 Instruction set summary
o 4.3.4 Architectural features
o 4.3.5 Implementation and featured application areas
* 4.4 ARCHITECTURE OF THE NOVIX NC4016
o 4.4.1 Introduction
o 4.4.2 Block diagram
o 4.4.3 Instruction set summary
o 4.4.4 Architectural features
o 4.4.5 Implementation and featured application areas
* 4.5 ARCHITECTURE OF THE HARRIS RTX 2000
o 4.5.1 Introduction
o 4.5.2 Block diagram
o 4.5.3 Instruction set summary
o 4.5.4 Architectural features
o 4.5.5 Implementation and featured application areas
o 4.5.6 Standard cell designs
CHAPTER 5: Architecture of 32-bit Systems
* 5.1 WHY 32-BIT SYSTEMS?
* 5.2 ARCHITECTURE OF THE FRISC 3 (SC32)
o 5.2.1 Introduction
o 5.2.2 Block diagram
o 5.2.3 Instruction set summary
o 5.2.4 Architectural features
o 5.2.5 Implementation and featured application areas
* 5.3 ARCHITECTURE OF THE RTX 32P
o 5.3.1 Introduction
o 5.3.2 Block diagram
o 5.3.3 Instruction set summary
o 5.3.4 Architectural features
o 5.3.5 Implementation and featured application areas
* 5.4 ARCHITECTURE OF THE SF1
o 5.4.1 Introduction
o 5.4.2 Block diagram
o 5.4.3 Instruction set summary
o 5.4.4 Architectural features
o 5.4.5 Implementation and featured application areas
CHAPTER 6: Understanding Stack Machines
* 6.1 AN HISTORICAL PERSPECTIVE
o 6.1.1 Register vs. non-register machines
o 6.1.2 High level language vs. RISC machines
* 6.2 ARCHITECTURAL DIFFERENCES FROM CONVENTIONAL MACHINES
o 6.2.1 Program size
o 6.2.2 Processor and system complexity
o 6.2.3 Processor performance
+ 6.2.3.1 Instruction execution rate
+ 6.2.3.2 System Performance
+ 6.2.3.3 Which programs are most suitable?
o 6.2.4 Program execution consistency
* 6.3 A STUDY OF FORTH INSTRUCTION FREQUENCIES
o 6.3.1 Dynamic instruction frequencies
o 6.3.2 Static instruction frequencies
o 6.3.3 Instruction compression on the RTX 32P
+ 6.3.3.1 Execution speed gains
+ 6.3.3.2 Memory size cost
* 6.4 STACK MANAGEMENT ISSUES
o 6.4.1 Estimating stack size: An experiment
o 6.4.2 Overflow handling
+ 6.4.2.1 A very large stack memory
+ 6.4.2.2 Demand fed single-element stack manager
+ 6.4.2.3 Paging stack manager
+ 6.4.2.4 An associative cache
* 6.5 INTERRUPTS AND MULTI-TASKING
o 6.5.1 Interrupt response latency
+ 6.5.1.1 Instruction restartability
o 6.5.2 Lightweight interrupts
o 6.5.3 Context switches
+ 6.5.3.1 A context switching experiment
+ 6.5.3.2 Multiple stack spaces for multi-tasking
CHAPTER 7: Software Issues
* 7.1 THE IMPORTANCE OF FAST SUBROUTINE CALLS
o 7.1.1 The importance of small procedures
o 7.1.2 The proper size for a procedure
o 7.1.3 Why programmers don't use small procedures
o 7.1.4 Architectural support for procedures
* 7.2 LANGUAGE CHOICE
o 7.2.1 Forth: strengths and weaknesses
o 7.2.2 C and other conventional languages
o 7.2.3 Rule-based systems and functional programming
* 7.3 UNIFORMITY OF SOFTWARE INTERFACES
CHAPTER 8: Applications
* 8.1 REAL TIME EMBEDDED CONTROL
o 8.1.1 Requirements of real time control
o 8.1.2 How stack machines meet these needs
* 8.2 16-BIT VERSUS 32-BIT HARDWARE
o 8.2.1 16-Bit hardware often best
o 8.2.2 32-Bit hardware is sometimes required
* 8.3 SYSTEM IMPLEMENTATION APPROACHES
o 8.3.1 Hardwired systems vs. microcoded systems
o 8.3.2 Integration level and system cost/performance
* 8.4 EXAMPLE APPLICATION AREAS
CHAPTER 9: The Future of Stack Computers
* 9.1 SUPPORT FOR CONVENTIONAL LANGUAGES
o 9.1.1 Stack frames
o 9.1.2 Aliasing of registers and memory
o 9.1.3 A strategy for handling stack frames
o 9.1.4 Conventional language execution efficiency
* 9.2 VIRTUAL MEMORY AND MEMORY PROTECTION
o 9.2.1 Memory protection is sometimes important
o 9.2.2 Virtual memory is not used in controllers
* 9.3 THE USE OF A THIRD STACK
* 9.4 THE LIMITS OF MEMORY BANDWIDTH
o 9.4.1 The history of memory bandwidth problems
o 9.4.2 Current memory bandwidth concerns
o 9.4.3 The stack machine solution
* 9.5 TWO IDEAS FOR STACK MACHINE DESIGN
o 9.5.1 Conditional subroutine returns
o 9.5.2 Use of the stack for holding code
* 9.6 THE IMPACT OF STACK MACHINES ON COMPUTING
Appendix A: A Survey of Computers with Hardware Stack Support
