今晚拼一枪！再翻译一节。原文链接https://azeria-labs.com/arm-conditional-execution-and-branching-part-6/

We already briefly touched the conditions’ topic while discussing the CPSR register. We use conditions for controlling the program’s flow during it’s runtime usually by making jumps (branches) or executing some instruction only when a condition is met. The condition is described as the state of a specific bit in the CPSR register. Those bits change from time to time based on the outcome of some instructions. For example, when we compare two numbers and they turn out to be equal, we trigger the Zero bit (Z = 1), because under the hood the following happens: a – b = 0. In this case we have equal condition. If the first number was bigger, we would have a GreaterThan condition and in the opposite case –LowerThan. There are more conditions, like Lower orEqual (LE),Greater orEqual (GE) and so on.

在讨论CPSR寄存器时，我们已经简要地讨论了条件的话题。当特定条件满足时，借助条件指令， 通过跳转（分支）或执行某些特定指令来控制程序的流动方向。相关条件被描述为CPSR寄存器中的特定位的状态，这些位根据指令计算后的结果实时改变。比如，如果我们比较两个数并且他们相等，就将零标志位置位 （Z=1） ，因为在系统底层发生了a-b=0。在这个例子里两个数是相等的，但如果第一个数字比第二个大，会得出大于结论。而相反的情况下得出小于结论。当然还有很多其他的条件，比如小于等于（LE），大于等于（GE）等等。

The following table lists the available condition codes, their meanings, and the status of the flags that are tested.

下表列出了可能的条件指令，他们的含义以及被检测的状态标志位

We can use the following piece of code to look into a practical use case of conditions where we perform conditional addition.

我们使用如下代码来实现条件相加指令：

The first CMP instruction in the code above triggers Negative bit to be set (2 – 3 = -1) indicating that the value in r0 is Lower Than number 3. Subsequently, the ADDLT instruction is executed because LT condition is full filled when V != N (values of overflow and negative bits in the CPSR are different). Before we execute second CMP, our r0 = 3. That’s why second CMP clears out Negative bit (because 3 – 3 = 0, no need to set the negative flag) and sets theZero flag (Z = 1). Now we have V = 0 and N = 0 which results in LT condition to fail. As a result, the second ADDLT is not executed and r0 remains unmodified. The program exits with the result 3.

代码中，第一个CMP比较指令执行后触发了N标志位的置位（2-3=-1），这表明r0的值比数字3要小。随后，由于LT条件满足， 即V != N（在CPSR里溢出标志位和负标志位不是同一个），所以执行了addlt指令。由于第二个cmp指令将N标志位清空（因为3-3=0，不需要置位N标志位），将零标志位置位（Z=0），现在 V = 0且 N = 0，从而导致LT条件不成立，结果就是第二个addlt没有执行，r0也没改变，程序退出并返回结果3 

In the Instruction Set chapter we talked about the fact that there are different Thumb versions. Specifically, the Thumb version which allows conditional execution (Thumb-2). Some ARM processor versions support the “IT” instruction that allows up to 4 instructions to be executed conditionally in Thumb state.

Reference: http://infoce·nter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABIJDIC.html

参考： http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABIJDIC.html 

Syntax: IT{x{y{z}}}cond    语法结构： IT{x{y{z}}} cond（译者注：xyz指IT后最多再跟三个大写字母，大写字母可以是T，可以是E，T就是then，E就是else）

cond specifies the condition for the first instruction in the IT block

cond规定了执行IT语句块里的第一条指令需要满足的条件

x specifies the condition switch for the second instruction in the IT block

x规定了执行的IT语句块中第二条指令需要满足的条件

y specifies the condition switch for the third instruction in the IT block

y规定了执行IT语句块里的第三条指令需要满足的条件

z specifies the condition switch for the fourth instruction in the IT block

z 规定了执行IT语句块里的第四条指令需要满足的条件

The structure of the IT instruction is “IF-Then-(Else)” and the syntax is a construct of the two letters T and E:

IT指令集的结构是： “IF-Then-(Else)”，它的语法结构由两个字母构成：

IT refers to If-Then (next instruction is conditional)

IT代表If-Then（下一条指令是条件指令）

ITT refers to If-Then-Then (next 2 instructions are conditional)

ITT代表If-Then-Then（接下来的两条指令是条件指令）

ITE refers to If-Then-Else (next 2 instructions are conditional)

ITE代表 If-Then-Else（接下来的两条指令是条件指令）

ITTE refers to If-Then-Then-Else (next 3 instructions are conditional)

ITTE代表 If-Then-Then-Else （接下来的三条指令是条件指令）

ITTEE refers to If-Then-Then-Else-Else (next 4 instructions are conditional)

ITTEE代表 If-Then-Then-Else-Else （接下来的四条指令是条件指令）

[培训]内核驱动高级班，冲击BAT一流互联网大厂工作，每周日13:00-18:00直播授课