翻译过程中的摘抄的笔记,应该少不了些错误。但愿你在配合此 笔记看原 TLBs, paging-structure cache, and their invalidation时可以指出那些 bugs。原文档中的主要部分, invalidation的翻译笔记没有包含在此处。
内容包括:
IA32的 paging流程说明
IA32的 转接(referenced)入 说明
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Processor implementations may limit the size of the physical addresses to less than 52 bits. The physical-address width supported is enumerated using CPUID. 也即理论上当前可支持的最大内存是4294967296 GB(2的52次方),但windows给出的上限是512 GB,此是由于架构的设计中 paging所要 查询的表着实太多了,性能要求放弃那种设计,无法分配太多的内存用来 page structures的储存.
IA32e是当前的 intel主要架构,它既向下兼容 32位的设计,也是 intel 64的实现方式,简而言之,现在的intel 64并没有象 线性地址 那样大刀阔斧的新设计,而是扩展的 32 bits方式 ,因此按intel的意思,了解IA32e的设计在当前是 最简单有效、最值得涉猎和拥有的架构 /:^]。
参看:
64-bit mode (sub-mode of IA-32e mode) — This mode enables a 64-bit
operating system to run applications written to access 64-bit linear address
space. For brevity, the 64-bit sub-mode is referred to as 64-bit mode in IA-32
architecture.
64-bit mode extends the number of general purpose registers and SIMD
extension registers from 8 to 16. General purpose registers are widened to 64
bits. The mode also introduces a new opcode prefix (REX) to access the register
extensions.
64-bit mode is enabled by the operating system on a code-segment basis. Its
default address size is 64 bits and its default operand size is 32 bits. The default
operand size can be overridden on an instruction-by-instruction basis using a REX
opcode prefix in conjunction with an operand size override prefix.
REX prefixes allow a 64-bit operand to be specified when operating in 64-bit
mode. By using this mechanism, many existing instructions have been promoted
to allow the use of 64-bit registers and 64-bit addresses.
注意,文档中的全是IA-32e mode下的流程。
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由线程地址得到物理内存的过程称为 对页(paging),是由软件实现的。CR0的bit 31(PG位)为1时才会在访问内存地址时进行 paging,不然为 实地址模式。
指令、数据指令对内存的访问都是通过线性地址定址的。IA-32和inter 64下任何对内存的访问都通过 线性地址定址,包括一些永远不会表现在 可执行代码中的 访问过程,此种访问无论何种情况下都不会引发 page faults(主要表现,缺页异常)。
具体的paging流程由 处理器的控制变量寄存器中和 paging mode相关的位决定。
• If PAE (bit 5) is 0 in control register CR4, paging translates from 32-bit linear addresses
to 32-bit physical addresses. (This mode can translate to 36-bit physical addresses, but
only for large pages.) 当前主要应用在32位总线的系统中
• If CR4.PAE = 1 and LMA (bit 10) is 0 in the IA32_EFER MSR, paging translates from
32-bit linear addresses to 36-bit physical addresses.
• If IA32_EFER.LMA = 1, paging translates from 48-bit linear addresses to 52-bit physical
addresses.1 This mode is called IA-32e mode. IA-32e mode is available only on
processors that support the Intel® 64 architecture. 当前主要应用在64位系统上
PAE和 LMA同时为空的情况不会出现,此前提有 处理器的保证。
Paging Mode PML4 PDP PDE PTE
IA32_EFER.LMA = 1 47:39 47:30 47:21 47:12
IA32_EFER.LMA = 0 and CR0.PAE = 1 N/A 31:30* 31:21 31:12
IA32_EFER.LMA = 0 and CR0.PAE = 0 N/A N/A 31:22 31:12
No PTE is used for large-page translations (if PS is 1 in the PDE);
*For this paging mode, these entries are called PDPTRs and are all loaded together.
n/a 表示不经过那流程